VHDL: slice a various part of an array -

i have std_logic_vector (0 639). on incoming signal have iterate through vector , next 2 bits of it.

i'm trying make like, integer counter:

counter := counter+1; myvar := data((counter*2) ((counter*2)+1)); 

i following:

error (10394): vhdl error @ module.vhd(227): left bound of range must constant

upd: following suggested @user1155120: writing every single bit of vector every single corresponding bit of myvar

myvar(0) := data(counter * 2); myvar(1) := data(counter * 2 + 1); 

works fine long use 2bit myvar, if want use 16-32-80bit variable? problem avoided, not solved.

googling shows error message quartus ii (see id: 10394). lrm reference provides isn't particularly helpful, it's limitation on synthesis can't define variable width word size multiplexer. not smart enough detect both bounds referenced counter.

what happens if express multiplexer each bit of myvar separately? (indexed name instead of slice name, 2 variable assignments myvar(1) , myvar(0)).

myvar(0) := data(counter * 2); myvar(1) := data(counter * 2 + 1); 

this thread need strange error" left bound of range must constant " suggests using loop assign each bit of target slice range, using indexed name on per element basis.

for in myvar'range loop     myvar(i) := data(counter * 2 + i); end loop; 

counter needs half index range, you're multiplying 2.