vhdl - Is there a way to show variables in ISim? -

i'm trying moniter state of variable:

shared variable div16 : integer := 0; 

but recieving error in isim:

isim not yet support tracing of vhdl variables.

can convert variable signal within testbench file? or there other way show value changing waveform?

complete code:

entity main_uart   generic (     divisor: natural := 120 -- divisor = 50,000,000 / (16 x baud_rate)     -- 9600 -> 120      -- 19200 -> 60   );   port (     clk: in std_logic;        -- clock     rst: in std_logic         -- reset   ); end main_uart;  architecture behavioral of main_uart      signal top16: std_logic; -- 1 clk spike @ 16x baud rate         shared variable div16 : integer := 0;  --  constant counter_bits : natural := integer(ceil(log2(real(divisor))));  begin  -- -------------------------- -- clk16 clock generation -- --------------------------     process (rst, clk)     begin         if rst='1'             top16 <= '0';  --good             div16 := 0;         elsif rising_edge(clk)             top16 <= '0';                 if div16 = divisor                     div16 := 0;                     top16 <= '1';  --good                 else                     div16 := div16 + 1;                 end if;         end if;     end process;  end behavioral; 

you can add:

signal div16_signal : integer := 0; 

and @ end of process add:

div16_signal <= div16;